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標題: 低成本誤碼測試儀設計 [列印本頁]

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作者: alphi    時間: 2012-5-4 12:36:10     標題: 低成本誤碼測試儀設計



一、前言
  在通訊系統中常常需要使用誤碼測試儀來判斷通訊品質好壞,但是通常一台要價不便宜以太克的BERTScope BSA125C 就至少要四百萬台幣
   
  而便宜一點的Centellax TG1B1 也要八十 幾萬


  當然另一種常見方式就是自行使用FPGA去製作相關功能.這樣就必須花費許多技術成本.以我為例使用Xilinx Virtex-6 一顆就要30000~40000元台幣(使用Xilinx 是因為他已經有相關的Application Notes,只要花時間去修改跟增加功能).最後就是本文採用現有 IC達到功能.

  本文中採用Maxim DS2174 E-BERT(增強型誤碼測試),其特性如下:
   (a) 位元率(Bit rate)最高可達 155Mbps
   (b) 測式樣式(Test Pattern):PRBS1~PRBS32
   (c) 使用者自訂樣式(User Define Pattern): 512bytes= 4096bits
   (d) 誤碼計數器:48bit (以155Mbps進行測試可以量測時間為504小時:2^48/155Mbps=504hours)
   (e) 支援誤碼插入(Error Injection)

二、原理
     Function Diagram如下圖所示
     

三、實做
由於想要產生5Mbps~155Mbps,所以採用VCO Oscillator 比較不適合,所以採用SiLabs公司出產的Low Jitter 4Channel AnyClock IC:SI5338A
SI5338 產生LVPECL Clock 相關程式碼,使用ATMEL AVR ATMEGA128A MCU

1. /*
   
2.                SI5338 副程式
   
3.                      使用ATMEL GCC Toolchain
   
4. */
   
5. #include <stdio.h>
   
6. #include <stdlib.h>
   
7. #include <math.h>
   
8. 
   
9. #include "si5338.h"
   
10. 
    
11. void SI5338_WriteData(uint8_t devid,uint8_t addr,uint8_t data)
    
12. {
    
13.         uint8_t status;
    
14.         status=TWI_Start();
    
15.         //_delay_ms(5);
    
16. 
    
17.         status=TWI_Write(devid);
    
18.         //_delay_ms(5);
    
19.        
    
20.         status=TWI_Write(addr);
    
21.         _delay_ms(5);
    
22. 
    
23. 
    
24.         status=TWI_Write(data);
    
25.         //_delay_ms(5);
    
26.        
    
27.         status=TWI_Stop();
    
28.         //_delay_ms(5);
    
29. }
    
30. 
    
31. 
    
32. 
    
33. 
    
34. void SI5338_Init(uint8_t devid)
    
35. {
    
36.         int16_t i;
    
37.         struct SI5338_RegMap        SI5338_RegData[NUM_REGS_MAX] ={
    
38.         {  0,0x00},
    
39. {  1,0x00},
    
40. {  2,0x00},
    
41. {  3,0x00},
    
42. {  4,0x00},
    
43. {  5,0x00},
    
44. {  6,0x08},
    
45. {  7,0x00},
    
46. {  8,0x70},
    
47. {  9,0x0F},
    
48. { 10,0x00},
    
49. { 11,0x00},
    
50. { 12,0x00},
    
51. { 13,0x00},
    
52. { 14,0x00},
    
53. { 15,0x00},
    
54. { 16,0x00},
    
55. { 17,0x00},
    
56. { 18,0x00},
    
57. { 19,0x00},
    
58. { 20,0x00},
    
59. { 21,0x00},
    
60. { 22,0x00},
    
61. { 23,0x00},
    
62. { 24,0x00},
    
63. { 25,0x00},
    
64. { 26,0x00},
    
65. { 27,0x70},
    
66. { 28,0x96},
    
67. { 29,0x90},
    
68. { 30,0xB0},
    
69. { 31,0xC0},
    
70. { 32,0xC0},
    
71. { 33,0xC0},
    
72. { 34,0xC0},
    
73. { 35,0x00},
    
74. { 36,0x04},
    
75. { 37,0x04},
    
76. { 38,0x04},
    
77. { 39,0x04},
    
78. { 40,0xEF},
    
79. { 41,0x3D},
    
80. { 42,0x2F},
    
81. { 43,0x00},
    
82. { 44,0x00},
    
83. { 45,0x00},
    
84. { 46,0x00},
    
85. { 47,0x14},
    
86. { 48,0x3A},
    
87. { 49,0x00},
    
88. { 50,0xC4},
    
89. { 51,0x07},
    
90. { 52,0x10},
    
91. { 53,0x00},
    
92. { 54,0x06},
    
93. { 55,0x00},
    
94. { 56,0x00},
    
95. { 57,0x00},
    
96. { 58,0x00},
    
97. { 59,0x01},
    
98. { 60,0x00},
    
99. { 61,0x00},
    
100. { 62,0x00},
     
101. { 63,0x10},
     
102. { 64,0x00},
     
103. { 65,0x06},
     
104. { 66,0x00},
     
105. { 67,0x00},
     
106. { 68,0x00},
     
107. { 69,0x00},
     
108. { 70,0x01},
     
109. { 71,0x00},
     
110. { 72,0x00},
     
111. { 73,0x00},
     
112. { 74,0x10},
     
113. { 75,0x6F},
     
114. { 76,0x05},
     
115. { 77,0x74},
     
116. { 78,0xC4},
     
117. { 79,0x07},
     
118. { 80,0x00},
     
119. { 81,0xCD},
     
120. { 82,0x15},
     
121. { 83,0x04},
     
122. { 84,0x00},
     
123. { 85,0x10},
     
124. { 86,0x5E},
     
125. { 87,0x07},
     
126. { 88,0xA8},
     
127. { 89,0x80},
     
128. { 90,0x00},
     
129. { 91,0x00},
     
130. { 92,0x85},
     
131. { 93,0xCF},
     
132. { 94,0x00},
     
133. { 95,0x00},
     
134. { 96,0x10},
     
135. { 97,0xC4},
     
136. { 98,0x2F},
     
137. { 99,0xF0},
     
138. {100,0x01},
     
139. {101,0x00},
     
140. {102,0x00},
     
141. {103,0x71},
     
142. {104,0x02},
     
143. {105,0x00},
     
144. {106,0x80},
     
145. {107,0x00},
     
146. {108,0x00},
     
147. {109,0x00},
     
148. {110,0x40},
     
149. {111,0x00},
     
150. {112,0x00},
     
151. {113,0x00},
     
152. {114,0x40},
     
153. {115,0x00},
     
154. {116,0x80},
     
155. {117,0x00},
     
156. {118,0x40},
     
157. {119,0x00},
     
158. {120,0x00},
     
159. {121,0x00},
     
160. {122,0x40},
     
161. {123,0x00},
     
162. {124,0x00},
     
163. {125,0x00},
     
164. {126,0x00},
     
165. {127,0x00},
     
166. {128,0x00},
     
167. {129,0x00},
     
168. {130,0x00},
     
169. {131,0x00},
     
170. {132,0x00},
     
171. {133,0x00},
     
172. {134,0x00},
     
173. {135,0x00},
     
174. {136,0x00},
     
175. {137,0x00},
     
176. {138,0x00},
     
177. {139,0x00},
     
178. {140,0x00},
     
179. {141,0x00},
     
180. {142,0x00},
     
181. {143,0x00},
     
182. {144,0x00},
     
183. {145,0x00},
     
184. {146,0xFF},
     
185. {147,0x00},
     
186. {148,0x00},
     
187. {149,0x00},
     
188. {150,0x00},
     
189. {151,0x00},
     
190. {152,0x00},
     
191. {153,0x00},
     
192. {154,0x00},
     
193. {155,0x00},
     
194. {156,0x00},
     
195. {157,0x00},
     
196. {158,0x00},
     
197. {159,0x00},
     
198. {160,0x00},
     
199. {161,0x00},
     
200. {162,0x00},
     
201. {163,0x00},
     
202. {164,0x00},
     
203. {165,0x00},
     
204. {166,0x00},
     
205. {167,0x00},
     
206. {168,0x00},
     
207. {169,0x00},
     
208. {170,0x00},
     
209. {171,0x00},
     
210. {172,0x00},
     
211. {173,0x00},
     
212. {174,0x00},
     
213. {175,0x00},
     
214. {176,0x00},
     
215. {177,0x00},
     
216. {178,0x00},
     
217. {179,0x00},
     
218. {180,0x00},
     
219. {181,0x00},
     
220. {182,0x00},
     
221. {183,0x00},
     
222. {184,0x00},
     
223. {185,0x00},
     
224. {186,0x00},
     
225. {187,0x00},
     
226. {188,0x00},
     
227. {189,0x00},
     
228. {190,0x00},
     
229. {191,0x00},
     
230. {192,0x00},
     
231. {193,0x00},
     
232. {194,0x00},
     
233. {195,0x00},
     
234. {196,0x00},
     
235. {197,0x00},
     
236. {198,0x00},
     
237. {199,0x00},
     
238. {200,0x00},
     
239. {201,0x00},
     
240. {202,0x00},
     
241. {203,0x00},
     
242. {204,0x00},
     
243. {205,0x00},
     
244. {206,0x00},
     
245. {207,0x00},
     
246. {208,0x00},
     
247. {209,0x00},
     
248. {210,0x00},
     
249. {211,0x00},
     
250. {212,0x00},
     
251. {213,0x00},
     
252. {214,0x00},
     
253. {215,0x00},
     
254. {216,0x00},
     
255. {217,0x00},
     
256. {218,0x00},
     
257. {219,0x00},
     
258. {220,0x00},
     
259. {221,0x0D},
     
260. {222,0x00},
     
261. {223,0x00},
     
262. {224,0xF4},
     
263. {225,0xF0},
     
264. {226,0x00},
     
265. {227,0x00},
     
266. {228,0x00},
     
267. {229,0x00},
     
268. {230,0x00},
     
269. {231,0x00},
     
270. {232,0x00},
     
271. {233,0x00},
     
272. {234,0x00},
     
273. {235,0x00},
     
274. {236,0x00},
     
275. {237,0x00},
     
276. {238,0x14},
     
277. {239,0x00},
     
278. {240,0x00},
     
279. {241,0x65},
     
280. {242,0x00},
     
281. {243,0xF0},
     
282. {244,0x00},
     
283. {245,0x00},
     
284. {246,0x00},
     
285. {247,0x00},
     
286. {248,0x00},
     
287. {249,0xA8},
     
288. {250,0x00},
     
289. {251,0x84},
     
290. {252,0x00},
     
291. {253,0x00},
     
292. {254,0x00},
     
293. {255,1},
     
294. {  0,0x00},
     
295. {  1,0x00},
     
296. {  2,0x00},
     
297. {  3,0x00},
     
298. {  4,0x00},
     
299. {  5,0x00},
     
300. {  6,0x00},
     
301. {  7,0x00},
     
302. {  8,0x00},
     
303. {  9,0x00},
     
304. { 10,0x00},
     
305. { 11,0x00},
     
306. { 12,0x00},
     
307. { 13,0x00},
     
308. { 14,0x00},
     
309. { 15,0x00},
     
310. { 16,0x00},
     
311. { 17,0x01},
     
312. { 18,0x00},
     
313. { 19,0x00},
     
314. { 20,0x90},
     
315. { 21,0x31},
     
316. { 22,0x00},
     
317. { 23,0x00},
     
318. { 24,0x01},
     
319. { 25,0x00},
     
320. { 26,0x00},
     
321. { 27,0x00},
     
322. { 28,0x00},
     
323. { 29,0x00},
     
324. { 30,0x00},
     
325. { 31,0x00},
     
326. { 32,0x00},
     
327. { 33,0x01},
     
328. { 34,0x00},
     
329. { 35,0x00},
     
330. { 36,0x90},
     
331. { 37,0x31},
     
332. { 38,0x00},
     
333. { 39,0x00},
     
334. { 40,0x01},
     
335. { 41,0x00},
     
336. { 42,0x00},
     
337. { 43,0x00},
     
338. { 44,0x00},
     
339. { 45,0x00},
     
340. { 46,0x00},
     
341. { 47,0x00},
     
342. { 48,0x00},
     
343. { 49,0x01},
     
344. { 50,0x00},
     
345. { 51,0x00},
     
346. { 52,0x90},
     
347. { 53,0x31},
     
348. { 54,0x00},
     
349. { 55,0x00},
     
350. { 56,0x01},
     
351. { 57,0x00},
     
352. { 58,0x00},
     
353. { 59,0x00},
     
354. { 60,0x00},
     
355. { 61,0x00},
     
356. { 62,0x00},
     
357. { 63,0x00},
     
358. { 64,0x00},
     
359. { 65,0x01},
     
360. { 66,0x00},
     
361. { 67,0x00},
     
362. { 68,0x90},
     
363. { 69,0x31},
     
364. { 70,0x00},
     
365. { 71,0x00},
     
366. { 72,0x01},
     
367. { 73,0x00},
     
368. { 74,0x00},
     
369. { 75,0x00},
     
370. { 76,0x00},
     
371. { 77,0x00},
     
372. { 78,0x00},
     
373. { 79,0x00},
     
374. { 80,0x00},
     
375. { 81,0x00},
     
376. { 82,0x00},
     
377. { 83,0x00},
     
378. { 84,0x90},
     
379. { 85,0x31},
     
380. { 86,0x00},
     
381. { 87,0x00},
     
382. { 88,0x01},
     
383. { 89,0x00},
     
384. { 90,0x00},
     
385. { 91,0x00},
     
386. { 92,0x00},
     
387. { 93,0x00},
     
388. { 94,0x00},
     
389. {255,0},
     
390. {246,2}};
     
391. 
     
392. 
     
393. 
     
394.         for(i=0;i<NUM_REGS_MAX;i++)
     
395.         {
     
396.                 SI5338_WriteData(devid,SI5338_RegData[i].Reg_Addr,SI5338_RegData[i].Reg_Val);
     
397.                 //_delay_ms(5);
     
398.         }
     
399.        
     
400. }
     
401. void SI5338_SetDatarate(uint8_t devid,float datarate)
     
402. {
     
403.         struct SI5338_RegMap SI5338_RegData[21];
     
404.         struct SI5338_clock_Setting Clock_set;
     
405. 
     
406.         float refclock=159.25248/(datarate+0.12);
     
407.        
     
408.        
     
409.         uint32_t Res=100000;
     
410.         uint32_t A=16;
     
411.         uint32_t B=0;
     
412.         uint32_t C=1;
     
413.         uint32_t INT;
     
414.         uint32_t DEC;
     
415.         uint32_t NUM;
     
416.         uint16_t i;
     
417. 
     
418.         A=(uint32_t)refclock;
     
419.         B=(uint32_t)((refclock-A)*(float)Res);
     
420.         C=Res;
     
421. 
     
422.         //FreqOut=2488.32/(float)A+(float)B/(float)C);
     
423.         INT=floor(128.0*(A*C+B)/C-512);
     
424.         NUM=(((128.0*((double)A*(double)C+(double)B)/(double)C)-floor(128.0*((double)A*(double)C+(double)B)/(double)C))*(double)C);
     
425.         DEC=C;
     
426.         NUM<<=2;
     
427. 
     
428.         Clock_set.INT_R2=(INT & 0xff);
     
429.         Clock_set.INT_R1=(INT>>=8 & 0xff);
     
430.         Clock_set.INT_R0=(INT>>=8 & 0xff);
     
431.        
     
432.         Clock_set.NUM_R3=(NUM & 0xff);
     
433.         Clock_set.NUM_R2=(NUM>>=8 & 0xff);
     
434.         Clock_set.NUM_R1=(NUM>>=8 & 0xff);
     
435.         Clock_set.NUM_R0=(NUM>>=8 & 0xff);
     
436.        
     
437.         Clock_set.DEC_R3=(DEC & 0xff);
     
438.         Clock_set.DEC_R2=(DEC>>=8 & 0xff);
     
439.         Clock_set.DEC_R1=(DEC>>=8 & 0xff);
     
440.         Clock_set.DEC_R0=(DEC>>=8 & 0xff);
     
441. 
     
442.         /*
     
443.                         Refernce Clock M0
     
444.         */
     
445.         //INT
     
446.         SI5338_RegData[0].Reg_Addr=53;
     
447.         SI5338_RegData[0].Reg_Val=Clock_set.INT_R2;
     
448.        
     
449.         SI5338_RegData[1].Reg_Addr=54;
     
450.         SI5338_RegData[1].Reg_Val=Clock_set.INT_R1;
     
451.        
     
452. 
     
453.         //NUM
     
454.         SI5338_RegData[2].Reg_Addr=55;
     
455.         SI5338_RegData[2].Reg_Val=Clock_set.NUM_R3|Clock_set.INT_R0;
     
456.        
     
457.         SI5338_RegData[3].Reg_Addr=56;
     
458.         SI5338_RegData[3].Reg_Val=Clock_set.NUM_R2;
     
459.        
     
460.         SI5338_RegData[4].Reg_Addr=57;
     
461.         SI5338_RegData[4].Reg_Val=Clock_set.NUM_R1;
     
462.        
     
463.         SI5338_RegData[5].Reg_Addr=58;
     
464.         SI5338_RegData[5].Reg_Val=Clock_set.NUM_R0;
     
465. 
     
466.         //DEN
     
467.         SI5338_RegData[6].Reg_Addr=59;
     
468.         SI5338_RegData[6].Reg_Val=Clock_set.DEC_R3;
     
469.        
     
470.         SI5338_RegData[7].Reg_Addr=60;
     
471.         SI5338_RegData[7].Reg_Val=Clock_set.DEC_R2;
     
472. 
     
473.         SI5338_RegData[8].Reg_Addr=61;
     
474.         SI5338_RegData[8].Reg_Val=Clock_set.DEC_R1;
     
475. 
     
476.         SI5338_RegData[9].Reg_Addr=62;
     
477.         SI5338_RegData[9].Reg_Val=Clock_set.DEC_R0;
     
478. 
     
479. 
     
480.         /*
     
481.                         Refernce Clock M1
     
482.         */
     
483. 
     
484.         //INT
     
485.         SI5338_RegData[10].Reg_Addr=64;
     
486.         SI5338_RegData[10].Reg_Val=Clock_set.INT_R2;
     
487. 
     
488.         SI5338_RegData[11].Reg_Addr=65;
     
489.         SI5338_RegData[11].Reg_Val=Clock_set.INT_R1;
     
490. 
     
491.         //SI5338_RegData[12].Reg_Addr=66;
     
492.         //SI5338_RegData[12].Reg_Val=Clock_set.INT_R0;
     
493. 
     
494.         //NUM
     
495.         SI5338_RegData[12].Reg_Addr=66;
     
496.         SI5338_RegData[12].Reg_Val=Clock_set.NUM_R3|Clock_set.INT_R0;
     
497. 
     
498.         SI5338_RegData[13].Reg_Addr=67;
     
499.         SI5338_RegData[13].Reg_Val=Clock_set.NUM_R2;
     
500. 
     
501.         SI5338_RegData[14].Reg_Addr=68;
     
502.         SI5338_RegData[14].Reg_Val=Clock_set.NUM_R1;
     
503. 
     
504.         SI5338_RegData[15].Reg_Addr=69;
     
505.         SI5338_RegData[15].Reg_Val=Clock_set.NUM_R0;
     
506. 
     
507.         //DEN
     
508.         SI5338_RegData[16].Reg_Addr=70;
     
509.         SI5338_RegData[16].Reg_Val=Clock_set.DEC_R3;
     
510. 
     
511.         SI5338_RegData[17].Reg_Addr=71;
     
512.         SI5338_RegData[17].Reg_Val=Clock_set.DEC_R2;
     
513. 
     
514.         SI5338_RegData[18].Reg_Addr=72;
     
515.         SI5338_RegData[18].Reg_Val=Clock_set.DEC_R1;
     
516. 
     
517.         SI5338_RegData[19].Reg_Addr=73;
     
518.         SI5338_RegData[19].Reg_Val=Clock_set.DEC_R0;
     
519. 
     
520.         SI5338_RegData[20].Reg_Addr=246;
     
521.         SI5338_RegData[20].Reg_Val=2;
     
522.    for(i=0;i<21;i++)
     
523.                 SI5338_WriteData(devid,SI5338_RegData[i].Reg_Addr,SI5338_RegData[i].Reg_Val);
     
524. }

複製代碼

Maxim DS2174 部分程式控制碼

1. #include <avr/io.h>
   
2. #include <avr/interrupt.h>
   
3. #include <util/delay>
   
4. 
   
5. #define EBERT_ENABLE()  (PORTF&=~(1<<0))
   
6. #define EBETT_DISABLE() (PORTF|=(1<<0))
   
7. 
   
8. #define RD_ENABLE()     (PORTF&=~(1<<1))
   
9. #define RD_DISABLE()    (PORTF|=(1<<1))
   
10. 
    
11. #define WR_ENABLE()     (PORTF&=~(1<<2))
    
12. #define WR_DISABLE()    (PORTF|=(1<<2))
    
13. 
    
14. void EBERT_WriteData(unsigned char reg,unsigned char data)
    
15. {
    
16.     EBERT_ENABLE();
    
17.     WR_ENABLE();
    
18.     PORTA=(reg & 0x0F); //4bit暫存器位址
    
19.     PORTD=data;         //8bit資料
    
20.     WR_DISABLE();
    
21.     EBERT_DISABLE();
    
22. }
    
23. unsigned char EBERT_ReadData(unsigned char reg)
    
24. {
    
25.     unsigned data;
    
26.     EBERT_ENABLE();
    
27.     RD_ENABLE();
    
28.     PORTA=(reg & 0x0F); //4bit暫存器位址
    
29.     data=PINE;         //8bit資料
    
30.     RD_DISABLE();
    
31.     EBERT_DISABLE();
    
32.    
    
33.     return data;
    
34. }
    
35. void EBERT_Init(void)
    
36. {
    
37.     BERT_WriteData(0x00,0x00); //Auto Resync,Pesudo Random Binrary Sequence
    
38.     BERT_WriteData(0x01,0x00); //Bit Mode,No Error Bit Inject
    
39.     BERT_WriteData(0x02,0x00); //No Error
    
40.     BERT_WriteData(0x03,0xFF); //Pattern Length
    
41.     BERT_WriteData(0x04,0x0C);
    
42.    
    
43. }
    
44. unsigned long long int EBERT_GetErrorCount(void)
    
45. {
    
46.     unisnged long long int ErrorCount=0;
    
47.    
    
48.     ErrorCount|=EBERT_ReadData(0x0A);
    
49.     ErrorCount|=EBERT_ReadData(0x0B)<<8;
    
50.     ErrorCount|=EBERT_ReadData(0x0C)<<16;
    
51.     ErrorCount|=EBERT_ReadData(0x0D)<<24;
    
52.     ErrorCount|=EBERT_ReadData(0x0E)<<32;
    
53.     ErrorCount|=EBERT_ReadData(0x0F)<<40;
    
54.    
    
55.     return ErrorCount;
    
56. }

複製代碼

四、測試波型


附件: TG1B1-A_picture__500_150.png (2012-5-4 10:54:57, 82.46 KB) / 下載次數 10
https://oursogo.com/forum.php?mod=attachment&aid=MjA4NDkzMnxhOWRiZDEyZHwxNzY0ODc3NDg0fDB8MA%3D%3D

附件: bertscope.jpg (2012-5-4 10:57:40, 10.08 KB) / 下載次數 14
https://oursogo.com/forum.php?mod=attachment&aid=MjA4NDkzM3xiZjIxMWIzNHwxNzY0ODc3NDg0fDB8MA%3D%3D

附件: DS2174.png (2012-5-4 11:10:21, 27.67 KB) / 下載次數 21
https://oursogo.com/forum.php?mod=attachment&aid=MjA4NTAyNnw5MmFmZDJmYnwxNzY0ODc3NDg0fDB8MA%3D%3D

附件: DS2174.png (2012-5-4 12:35:29, 255.96 KB) / 下載次數 17
https://oursogo.com/forum.php?mod=attachment&aid=MjA4NTYzMXwyMWJmYjdjNXwxNzY0ODc3NDg0fDB8MA%3D%3D

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