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標題: 脈衝偵測電路 [列印本頁]

作者: mm117777 時間: 2012-7-14 10:34:06 標題: 脈衝偵測電路

Verilog 程式：ptd.v
`timescale 10ns/1ns

module ptd(input clk, output ppulse);

not g1(nclkd, clk);
nand g2(npulse, nclkd, clk);
not g3(ppulse, npulse);

endmodule

module main;
reg clk;
wire p;

ptd ptd1(clk, p);

initial begin
  clk = 0;
end

always #1 begin
clk = clk + 1;
$monitor("%dns monitor: clk=%b p=%d", $stime, clk, p);
end

initial #100 $finish;

endmodule
執行結果
D:\ccc101\Verilog>iverilog ptd.v - o ptd

D:\ccc101\Verilog>vvp ptd
      1ns monitor: clk=1 p=0
      2ns monitor: clk=0 p=0
      3ns monitor: clk=1 p=0
      4ns monitor: clk=0 p=0
      5ns monitor: clk=1 p=0
      6ns monitor: clk=0 p=0
      7ns monitor: clk=1 p=0
      8ns monitor: clk=0 p=0
      9ns monitor: clk=1 p=0
      10ns monitor: clk=0 p=0
      11ns monitor: clk=1 p=0
      12ns monitor: clk=0 p=0
      13ns monitor: clk=1 p=0
      14ns monitor: clk=0 p=0
      15ns monitor: clk=1 p=0
      16ns monitor: clk=0 p=0
      17ns monitor: clk=1 p=0
      18ns monitor: clk=0 p=0
      19ns monitor: clk=1 p=0
      20ns monitor: clk=0 p=0
      21ns monitor: clk=1 p=0
      22ns monitor: clk=0 p=0
      23ns monitor: clk=1 p=0
      24ns monitor: clk=0 p=0
      25ns monitor: clk=1 p=0
      26ns monitor: clk=0 p=0
      27ns monitor: clk=1 p=0
      28ns monitor: clk=0 p=0
      29ns monitor: clk=1 p=0
      30ns monitor: clk=0 p=0
      31ns monitor: clk=1 p=0
      32ns monitor: clk=0 p=0
      33ns monitor: clk=1 p=0
      34ns monitor: clk=0 p=0
      35ns monitor: clk=1 p=0
      36ns monitor: clk=0 p=0
      37ns monitor: clk=1 p=0
      38ns monitor: clk=0 p=0
      39ns monitor: clk=1 p=0
      40ns monitor: clk=0 p=0
      41ns monitor: clk=1 p=0
      42ns monitor: clk=0 p=0
      43ns monitor: clk=1 p=0
      44ns monitor: clk=0 p=0
      45ns monitor: clk=1 p=0
      46ns monitor: clk=0 p=0
      47ns monitor: clk=1 p=0
      48ns monitor: clk=0 p=0
      49ns monitor: clk=1 p=0
      50ns monitor: clk=0 p=0
      51ns monitor: clk=1 p=0
      52ns monitor: clk=0 p=0
      53ns monitor: clk=1 p=0
      54ns monitor: clk=0 p=0
      55ns monitor: clk=1 p=0
      56ns monitor: clk=0 p=0
      57ns monitor: clk=1 p=0
      58ns monitor: clk=0 p=0
      59ns monitor: clk=1 p=0
      60ns monitor: clk=0 p=0
      61ns monitor: clk=1 p=0
      62ns monitor: clk=0 p=0
      63ns monitor: clk=1 p=0
      64ns monitor: clk=0 p=0
      65ns monitor: clk=1 p=0
      66ns monitor: clk=0 p=0
      67ns monitor: clk=1 p=0
      68ns monitor: clk=0 p=0
      69ns monitor: clk=1 p=0
      70ns monitor: clk=0 p=0
      71ns monitor: clk=1 p=0
      72ns monitor: clk=0 p=0
      73ns monitor: clk=1 p=0
      74ns monitor: clk=0 p=0
      75ns monitor: clk=1 p=0
      76ns monitor: clk=0 p=0
      77ns monitor: clk=1 p=0
      78ns monitor: clk=0 p=0
      79ns monitor: clk=1 p=0
      80ns monitor: clk=0 p=0
      81ns monitor: clk=1 p=0
      82ns monitor: clk=0 p=0
      83ns monitor: clk=1 p=0
      84ns monitor: clk=0 p=0
      85ns monitor: clk=1 p=0
      86ns monitor: clk=0 p=0
      87ns monitor: clk=1 p=0
      88ns monitor: clk=0 p=0
      89ns monitor: clk=1 p=0
      90ns monitor: clk=0 p=0
      91ns monitor: clk=1 p=0
      92ns monitor: clk=0 p=0
      93ns monitor: clk=1 p=0
      94ns monitor: clk=0 p=0
      95ns monitor: clk=1 p=0
      96ns monitor: clk=0 p=0
      97ns monitor: clk=1 p=0
      98ns monitor: clk=0 p=0
      99ns monitor: clk=1 p=0
   100ns monitor: clk=0 p=0

附件: ptd.jpg (2012-7-14 10:33:49, 15.56 KB) / 下載次數 31
https://oursogo.com/forum.php?mod=attachment&aid=MjYyNjQ0OHxiMGE1YWY2YnwxNzM5MjY2NTc2fDB8MA%3D%3D

作者: k302296 時間: 2012-7-15 22:19:59

我最近有接觸一些電路方面的東西，但是我始終不能理解CLK 到底是何用?
忽略那條線似乎並不會有太大差異??

作者: mm117777 時間: 2012-7-15 22:34:29

本帖最後由 mm117777 於 2012-7-15 22:35 編輯

reg clk
除法器
define NUM_STATE_BITS 2
`define IDLE 2'b00
`define INIT 2'b01
`define COMPUTE1 2'b10
`define COMPUTE2 2'b11

module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;

initial
clk = 0;

always
#50 clk = ~clk;

always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;

endmodule

module slow_div_system(pb,ready,x,y,r2,sysclk);
input pb,x,y,sysclk;
output ready,r2;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
ready = 1;
if (pb)
begin
@(posedge sysclk) enter_new_state(`INIT);
r2 <= @(posedge sysclk) 0;
while (r1 >= y)
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1 - y;
@(posedge sysclk) enter_new_state(`COMPUTE2);
r2 <= @(posedge sysclk) r2 + 1;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready);
endmodule

module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 14;
y = 7;
#250;
@(posedge sysclk);
for (x=14; x<=14; x = x+1)
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x/y === quotient)
$display("ok");
else
$display("error x=%d y=%d x/y=%d quotient=%d",x,y,x/y,quotient);
end
$stop;
end
endmodule
乘法器

`define NUM_STATE_BITS 2
`define IDLE 2'b00
`define INIT 2'b01
`define COMPUTE1 2'b10
`define COMPUTE2 2'b11

module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;

initial
clk = 0;

always
#50 clk = ~clk;

always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;

endmodule

module slow_div_system(pb,ready,x,y,r2,sysclk);
input pb,x,y,sysclk;
output ready,r2;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
ready = 1;
if (pb)
begin
@(posedge sysclk) enter_new_state(`INIT);
r2 <= @(posedge sysclk) 0;
while (r1 > 0)
begin
@(posedge sysclk) enter_new_state(`COMPUTE1);
r1 <= @(posedge sysclk) r1 - 1;
@(posedge sysclk) enter_new_state(`COMPUTE2);
r2 <= @(posedge sysclk) r2 + y;
end
end
end
task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d pb=%b ready=%b", $time, r1,r2, pb, ready);
endmodule

module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 5;
y = 3;
#250;
@(posedge sysclk);
for (x=5; x<=5; x=x+1)
begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x*y === quotient)
$display("ok");
else
$display("error x=%d y=%d x/y=%d quotient=%d",x,y,x/y,quotient);
end
$stop;
end
endmodule
==========================
這是由除法器改成的乘法器
目前測試應該沒問題

verilog複習

程式碼
===========

module top;
reg a,b;
wire c;
assign c=a&b; (加法器)
initial
begin
a=0; (初始值)
b=0;
#2000 $finish; (run的時間2us)
end
always
#50 a=~a; (每50ns作一次01改變)
always
#100 b=~b;
endmodule (結束模擬)

=

作者: alphi 時間: 2012-8-5 15:35:24

k302296 發表於 2012-7-15 22:19
我最近有接觸一些電路方面的東西，但是我始終不能理解CLK 到底是何用?
忽略那條線似乎並不會有太大差異?? ...

CLK為Clock(時脈簡寫)主要用來同步雙方動作,未來你接觸到的數位訊號很多都是同步訊號例如
I2C
SPI
MII
UART
ISO7816
...
那為什麼要同步訊號呢,簡單說就是讓雙方動作一致知道你要做什麼.否則對方怎麼知道你此時是在做什麼或者狀態為何.假設我有一筆資料為10001100,沒有同步訊號我就不知道當時該是0/1(或許你可以用timer計算一個bit 的等待時間為何?)但是這樣比較複雜.使用Clock 當她有訊號我就可以去判斷當時的狀態為何

作者: sv_swinger 時間: 2012-8-7 19:26:00

你的脈衝偵測電路在寫什麼啊？這樣能工作嗎？

只要把 clk 拿來稍微 delay 一下，再和原來的 clk 做 XOR 就好了啊，這是標準的 clock edge detector。

範例如下，時間單位就不寫了，假設 delay 遠小於 clock duration 。

module pulse_edge_detect (clk, clk_edge);
input clk;
output clk_edge;

wire delayed_clk, clk_edge;
assign delayed_clk = #0.01 clk;
assign clk_edge = clk ^ delayed_clk;

endmodule

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