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標題: 計數器 [列印本頁]

作者: mm117777 時間: 2012-7-14 10:36:58 標題: 計數器

Verilog 程式模組
module counter(input clk, rst, output reg [2:0] q);
always @(posedge clk) begin
      if (rst)
         q = 3'b000;
      else
         q = q+1;
end
endmodule
Verilog 測試程式
`timescale 1ns/10ps

module counterTest;
reg clk;
reg rst;
wire [2:0] q;

counter DUT (.clk(clk), .rst(rst), .q(q));

initial
begin
  clk = 0;
  rst = 1;
end

initial #100 rst = 0;

always #50 clk=clk+1;

endmodule
執行結果

程式：針對 Icarus 修改的
檔案：counter.v

module counter(input clk, rst, output reg [2:0] q);
always @(posedge clk) begin
      if (rst)
         q = 3'b000;
      else
         q = q+1;
end
endmodule

module counterTest;
reg clk;
reg rst;
wire [2:0] q;

counter DUT (.clk(clk), .rst(rst), .q(q));

initial
begin
  clk = 0;
  rst = 1;
end

initial #100 rst = 0;

always #50 clk=clk+1;

always @(negedge clk) begin
$display("q=%d", q);
end

initial #2000 $finish;

endmodule
Icarus 執行結果
D:\ccc101\icarus\ccc>iverilog -o count count.v

D:\ccc101\icarus\ccc>vvp count
q=0
q=1
q=2
q=3
q=4
q=5
q=6
q=7
q=0
q=1
q=2
q=3
q=4
q=5
q=6
q=7
q=0
q=1
q=2
q=3

附件: medium.jpg (2012-7-14 10:36:26, 22.83 KB) / 下載次數 15
https://oursogo.com/forum.php?mod=attachment&aid=MjYyNjQ1Mnw0NWM3ZDY0Y3wxNzM5MjcyMDk3fDB8MA%3D%3D

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