-----------------------------------------------------------------------------------------------------------------------------
nsigned int results[3];
void main(void)
{
volatile unsigned int i; // Use volatile to prevent removal
// by compiler optimization
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
SD24CTL = SD24REFON+SD24SSEL0; // 1.2V ref, SMCLK
SD24CCTL0 = SD24SNGL+SD24GRP; // Single conv, group with CH1
SD24CCTL1 = SD24SNGL+SD24GRP; // Single conv, group with CH2
SD24CCTL2 = SD24SNGL+SD24IE; // Single conv, enable interrupt
for (i = 0; i < 0x3600; i++); // Delay for 1.2V ref startup
while (1)
{
SD24CCTL2 |= SD24SC; // SET BREAKPOINT HERE
// Set bit to start conversion
__bis_SR_register(LPM0_bits+GIE); // Enter LPM0 w/ interrupts
}
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=SD24_VECTOR
__interrupt void SD24AISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(SD24_VECTOR))) SD24AISR (void)
#else
#error Compiler not supported!
#endif
{
switch (SD24IV)
{
case 2: // SD24MEM Overflow
break;
case 4: // SD24MEM0 IFG
break;
case 6: // SD24MEM1 IFG
break;
case 8: // SD24MEM2 IFG
results[0] = SD24MEM0; // Save CH0 results (clears IFG)
results[1] = SD24MEM1; // Save CH1 results (clears IFG)
results[2] = SD24MEM2; // Save CH2 results (clears IFG)
break;
}