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SR 閂鎖器
module latch(input Sbar, Rbar, output Q, Qbar);
nand g1(Q, Sbar, Qbar);
nand g2(Qbar, Rbar, Q);
endmodule
module main;
reg Sbar, Rbar;
wire Q, Qbar;
latch DUT(Sbar, Rbar, Q, Qbar);
initial
begin
Sbar = 0;
Rbar = 0;
end
always #50 begin
Sbar = Sbar+1;
$monitor("%4dns monitor: Sbar=%d Rbar=%d Q=%d Qbar=%d",
$stime, Sbar, Rbar, Q, Qbar);
end
always #100 begin
Rbar = Rbar + 1;
end
initial #1000 $finish;
endmodule
Icarus 執行結果
D:\ccc101\Verilog>iverilog latch.v -o latch
D:\ccc101\Verilog>vvp latch
50ns monitor: Sbar=1 Rbar=0 Q=0 Qbar=1
100ns monitor: Sbar=0 Rbar=1 Q=1 Qbar=0
150ns monitor: Sbar=1 Rbar=1 Q=1 Qbar=0
200ns monitor: Sbar=0 Rbar=0 Q=1 Qbar=1
250ns monitor: Sbar=1 Rbar=0 Q=0 Qbar=1
300ns monitor: Sbar=0 Rbar=1 Q=1 Qbar=0
350ns monitor: Sbar=1 Rbar=1 Q=1 Qbar=0
400ns monitor: Sbar=0 Rbar=0 Q=1 Qbar=1
450ns monitor: Sbar=1 Rbar=0 Q=0 Qbar=1
500ns monitor: Sbar=0 Rbar=1 Q=1 Qbar=0
550ns monitor: Sbar=1 Rbar=1 Q=1 Qbar=0
600ns monitor: Sbar=0 Rbar=0 Q=1 Qbar=1
650ns monitor: Sbar=1 Rbar=0 Q=0 Qbar=1
700ns monitor: Sbar=0 Rbar=1 Q=1 Qbar=0
750ns monitor: Sbar=1 Rbar=1 Q=1 Qbar=0
800ns monitor: Sbar=0 Rbar=0 Q=1 Qbar=1
850ns monitor: Sbar=1 Rbar=0 Q=0 Qbar=1
900ns monitor: Sbar=0 Rbar=1 Q=1 Qbar=0
950ns monitor: Sbar=1 Rbar=1 Q=1 Qbar=0
1000ns monitor: Sbar=0 Rbar=0 Q=1 Qbar=1
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發表於 2012-7-14 10:32:22
