[問題求助] Verilog問題... [複製連結]

module OSC1M(clk_in,clk_1M);
  input   clk_in;
  output  clk_1M;
  wire    clk_in,clk_1M;
  reg     [4:0]count=5'h00;
  
  always @(posedge clk_in)
    begin
      count = count+1;
      clk_1M = count[4];
    end
endmodule

`timescale 1ms/100ms
module SOC1M_tb;
  SOC1M dex(.clkin(clkin),.clkout(clkout));
  parameter hperi=40;
  
  initial begin
    clkin=1'b0;
  end
  
  always begin
    forever # hperi clkin=~clkin;
  end
  
endmodule