多工器

mm117777

Verilog 程式
module mux4(input[1:0]  select, input[3:0] d, output reg q );
always @( select or d )
begin
   case( select )
       0 : q = d[0];
       1 : q = d[1];
       2 : q = d[2];
       3 : q = d[3];
   endcase
end
endmodule

module main;
reg [3:0] d;
reg [1:0] s;
wire q;

mux4 DUT (s, d, q);

initial
begin
  s = 0;
  d = 4'b0110;
end

always #50 begin
  s=s+1;
  $monitor("%4dns monitor: s=%d d=%d q=%d", $stime, s, d, q);
end

initial #1000 $finish;

endmodule
Icarus 執行結果
D:\ccc101\icarus>iverilog mux4.v -o mux4

D:\ccc101\icarus>vvp mux4
  50ns monitor: s=1 d= 6 q=1
100ns monitor: s=2 d= 6 q=1
150ns monitor: s=3 d= 6 q=0
200ns monitor: s=0 d= 6 q=0
250ns monitor: s=1 d= 6 q=1
300ns monitor: s=2 d= 6 q=1
350ns monitor: s=3 d= 6 q=0
400ns monitor: s=0 d= 6 q=0
450ns monitor: s=1 d= 6 q=1
500ns monitor: s=2 d= 6 q=1
550ns monitor: s=3 d= 6 q=0
600ns monitor: s=0 d= 6 q=0
650ns monitor: s=1 d= 6 q=1
700ns monitor: s=2 d= 6 q=1
750ns monitor: s=3 d= 6 q=0
800ns monitor: s=0 d= 6 q=0
850ns monitor: s=1 d= 6 q=1
900ns monitor: s=2 d= 6 q=1
950ns monitor: s=3 d= 6 q=0
1000ns monitor: s=0 d= 6 q=0